Responsibilities
- design planning,
- logical synthesis,
- SDC development and validation,
- timing closure (STA),
- power planning,
- low power design techniques implementation,
- physical aware synthesis,
- conformal checks
Requirements
- Digital design flow knowledge RTL2GDS.
- Verilog/SystemVerilog;
- SDC development experience;
- Tcl/Python/shell knowledgw;
- GIT experience;
- Linux CLI;
- English – intermediate.
Key-wordsASIC, SoC, Front-end, STA, RTL, Verilog, Cadence, Synopsys, Genus, Modus
Tools knowledge
- Synopsys Design Compiler, Cadence Genus;
- Synopsys Formality, Cadence Conformal;
- Synopsys VCS, Cadence Incisive/Xcelium;
- Synopsys PrimeTime, Cadence Tempus